Intermediate Verification Model Bridges High And Low Levels Of Abstraction A Transaction - Oriented Approach Provides Benefits For Interfacing An Untimed

The ability to carry over models and testbenches from one level of abstraction to another is becoming increasingly important to the design and verification of system designs. This capability delivers the benefits of reuse with a scalable methodology. It therefore enables engineering teams to leverage the particular strengths of different modeling domains. For example, take the behavioral testbenches or system-reference models that are developed in a high-level verification language (HVL) [1,2,4]. They can be reused to verify the designunder-test (DUT) hardware models described in a hardware description language (HDL). But an intermediate modeling level is required to bridge these two levels of abstraction.